1. Field of the Invention
The present invention relates generally to an image data processing circuit having a shared memory, and more particularly, to such an image data processing circuit that a first image data processing circuit and a second image data processing circuit which are asynchronously operated share a memory.
2. Description of the Prior Art
Description is made by taking a facsimile as an example. The facsimile generally comprises an input image processing circuit serving as a first image data processing circuit and an image output processing circuit serving as a second image data processing circuit. The input image processing circuit drives an image sensor and processes document image data read by the image sensor. The image output processing circuit processes the image data to correspond to a recording device such as a printer and drives the recording device to record an image on paper or the like.
Meanwhile, in the facsimile, input image processing is processing required to read a document image and transmit the same to the other side of the communication through a telephone line or the like, which is separate processing from image output processing for recording an image on paper or the like, so that there is no necessity of synchronously performing the input image processing and the image output processing. Therefore, as the grade of the facsimile becomes higher, there have been requests such as a request that while an image is being recorded on paper or the like, a new document image is read by the image sensor and a request that while a document image is being read by the image sensor, another image is recorded on paper or the like.
On the other hand, in the input image processing and the image output processing, a memory for storing processed images once is indispensable. Therefore, the facsimile in which the input image processing and the image output processing are asynchronously performed has been conventionally provided with separate memories for the input image processing and the image output processing.
If memories are respectively provided for the input image processing and the image output processing, however, the cost of a circuit for the input image processing and the image output processing is high due to the memories.
When there are provided the input image processing circuit and the image output processing circuit which are asynchronously operated, therefore, the following constructions have been so adopted that a necessary memory can be shared between both the circuits. Specifically:
A. Such construction that the input image processing circuit and the image output processing circuit which are asynchronously operated are not simultaneously operated, or
B. Such construction that an arbitrating circuit is provided in order that the input image processing circuit and the image output processing circuit do not simultaneously access the memory.
The above described construction B will be described more concretely with reference to a block diagram of FIG. 4.
A shared memory (for example, a static random access memory: SRAM) 3 is connected to an input image processing circuit 1 and an image output processing circuit 2. In addition, an arbitrating circuit 4 is connected to the input image processing circuit 1 and the image output processing circuit 2. The arbitrating circuit 4 judges whether or not the image output processing circuit 2 is accessing the memory 3 when a memory request signal REQ1 is applied from, for example, the input image processing circuit 1, and sends to the input image processing circuit 1 an acknowledgment signal ACK1 indicating that access to the memory 3 for a predetermined time period t1 is allowed when the image output processing circuit 2 is not accessing the memory 3. Correspondingly, the input image processing circuit 1 accesses the memory 3 for the predetermined time period t1. When the input image processing circuit 1 continues to access the memory 3, it outputs the memory request signal REQ1 to the arbitrating circuit 4 again and waits to access the memory 3 until the acknowledgment signal ACK1 is sent from the arbitrating circuit 4.
Similarly, when the image output processing circuit 2 accesses the memory 3, it first outputs a memory request signal REQ2 to the arbitrating circuit 4. The image output processing circuit 2 can access the memory 3 for a predetermined time period t2 after an acknowledgment signal ACK 2 indicating that access to the memory 3 is allowed is applied from the arbitrating circuit 4.
Meanwhile, the unit time periods t1 and t2 during which the input image processing circuit 1 and the image output processing circuit 2 can respectively access the memory 3 are predetermined.
Consequently, timing at which and a time period during which the input image processing circuit 1 accesses the memory 3 and timing at which and a time period during which the image output processing circuit 2 accesses the memory 3 are so arbitrated by the arbitrating circuit 4 as not to be overlapped with each other.
When the construction A out of the above described conventional constructions is adopted, the input image processing and the image output processing cannot be simultaneously performed, so that the function of an apparatus adopting the construction A is limited. For example, in the facsimile, the function is so limited that an image cannot be recorded on paper while a document for transmission is being read, while a document for transmission cannot be read while an image is being recorded on paper.
On the other hand, when the construction B is adopted, the scale of an entire circuit for image data processing is increased because a complicated arbitrating circuit is required, although the input image processing circuit and the image output processing circuit can be simultaneously operated. In addition, if the arbitrating circuit is provided, the input image processing circuit and the image output processing circuit must output the memory request signals to the arbitrating circuit and wait for the acknowledgment signals from the arbitrating circuit before they access the memory, so that the processing speed is reduced.